\documentclass{article}
\usepackage[utf8]{inputenc}
\usepackage{tikz,german,graphicx}
\usepackage[landscape=true]{geometry}
\usetikzlibrary{circuits.logic.IEC, positioning}
\usetikzlibrary{arrows , automata , positioning}
\usepackage[utf8]{inputenc}

\begin{document}
\section{Zustandsdiagramm}
\begin{center}
\begin{tikzpicture}[>=stealth',shorten >=1pt,auto,node distance=2.5cm]
%Knoten
\node (0) [state, thick] {0};
\node (1) [state, thick, right of= 0] {1};
\node (2) [state, thick, above of= 1, right of= 1] {2};
\node (3) [state, thick, above of= 2, right of= 0] {3};

%Verbindungen
\path[thick,->]
(0) edge [bend angle=20, bend left,below] node {0/2} (2)
(0) edge [bend angle=25, bend right,above] node {1/1} (1)
(1) edge [loop] node {0/2} (1)
(1) edge [bend angle=50, bend left,below] node {1/1} (0)
(2) edge [bend angle=40, bend left,above] node {0/2} (3)
(2) edge [loop] node {1/3} (2)
(3) edge [bend angle=50, bend right,above] node {0/3} (0)
(3) edge [loop] node {1/0} (3)
;
\end{tikzpicture}
\end{center}
\section{Zustandstabelle}
\begin{center}
\begin{tabular}{|l|l|l|l||l|l|l|l|}
\hline
Zustand&     Eingabe&     Ausgabe   &  Folgezustand   &     z3+ &z2+& z1+ &z0+\\
\hline
\hline
0      &     0      &     2          & 2               &    0  & 1  & 0  & 0\\
0      &     1 &          1        &   1                &   0 &  0  & 1  & 0\\
1      &     0 &          2      &     1                 &  0 &  0  & 1  & 0\\
1      &     1 &          1       &    0                  & 0 &  0  & 0  & 1\\
2      &     0 &          2     &      3              &     1 &  0  & 0  & 0\\
2      &     1  &         3    &       2               &    0 &  1  & 0  & 0\\
3      &     0  &         3   &        0                &   0 &  0 &  0  & 1\\
3      &     1   &        0  &         3                 &  1 &  0 &  0  & 0\\
\hline
\end{tabular}
\end{center}
\section{Funktionsgleichung}
\begin{center}
\begin{verbatim}
                            z3+ := (z2 and not x) or (z3 and x)
                            z2+ := (z0 and not x) or (z2 and x)
                            z1+ := (z0 and x) or (z1 and not x)
                            z0+ := (z1 and x) or (z3 and not x)
                            y1 := (z0 and not x) or
                                (z1 and not x) or
                                (z2 and not x) or
                                (z2 and x) or
                                (z3 and not x)
                            y0 := (z0 and x) or
                                (z1 and x) or
                                (z2 and x) or
                                (3 and not x)
\end{verbatim}
\end{center}
\section{Schaltplan "Ubergangsschaltnetz}
\begin{center}
\tikzstyle{branch}=[fill,shape=circle,minimum size=3pt,inner sep=0pt]
\begin{tikzpicture}[scale=1.3, transform shape,circuit logic IEC]




% Eingangsvariablen
\node (z3) at (0,1) {$z_3$};
\node (z2) at (2,1) {$z_2$};
\node (z1) at (4,1) {$z_1$};
\node (z0) at (6,1) {$z_0$};
\node (x) at (8,1) {$x$};
\node (z0s) at (12,-1) {$z_0+$};
\node (z1s) at (12,-3.4) {$z_1+$};
\node (z2s) at (12,-6.2) {$z_2+$};
\node (z3s) at (12,-8.6) {$z_3+$};



% Gatter
\node[not gate] at ($(z3)+(1,-1)$) (notz3) {};
\node[not gate] at ($(z2)+(1,-1)$) (notz2) {};
\node[not gate] at ($(z1)+(1,-1)$) (notz1) {};
\node[not gate] at ($(z0)+(1,-1)$) (notz0) {};
\node[not gate] at ($(x)+(1,-1)$) (notx) {};

\node [and gate] at (10, -1) (andz01) {};
\node [and gate] at (10, -2.2) (andz02) {};
\node [and gate] at (10, -3.4) (andz11) {};
\node [and gate] at (10, -4.8) (andz12) {};
\node [and gate] at (10, -6.2) (andz21) {};
\node [and gate] at (10, -7.4) (andz22) {};
\node [and gate] at (10, -8.6) (andz31) {};
\node [and gate] at (10, -9.8) (andz32) {};

\node [or gate] at ($(andz01)+(1,0)$) (orz0) {};
\node [or gate] at ($(andz11)+(1,0)$) (orz1) {};
\node [or gate] at ($(andz21)+(1,0)$) (orz2) {};
\node [or gate] at ($(andz31)+(1,0)$) (orz3) {};


\draw (z3) |- (notz3);
\draw (z2) |- (notz2);
\draw (z1) |- (notz1);
\draw (z0) |- (notz0);
\draw (x) |- (notx);

\draw (andz01.output) |- (orz0.input 1);
\draw (andz02.output) |- (orz0.input 2);
\draw (andz11.output) |- (orz1.input 1);
\draw (andz12.output) |- (orz1.input 2);
\draw (andz21.output) |- (orz2.input 1);
\draw (andz22.output) |- (orz2.input 2);
\draw (andz31.output) |- (orz3.input 1);
\draw (andz32.output) |- (orz3.input 2);
\draw (orz3.output) |- (z3s);
\draw (orz2.output) |- (z2s);
\draw (orz1.output) |- (z1s);
\draw (orz0.output) |- (z0s);




\draw (notz0.output) |- (andz01.input 2);
\draw (notx.output) |- (andz01.input 1);

\draw (z3) |- (andz02.input 2);
\draw (x) |- (andz02.input 1);

\draw (z2) |- (andz11.input 1);
\draw (notx.output) |- (andz11.input 2);

\draw (z3) |- (andz12.input 1);
\draw (x) |- (andz12.input 2);

\draw (z0) |- (andz21.input 1);
\draw (x) |- (andz21.input 2);

\draw (z1) |- (andz22.input 1);
\draw (notx.output) |- (andz22.input 2);

\draw (z1) |- (andz31.input 1);
\draw (x) |- (andz31.input 2);

\draw (z3) |- (andz32.input 1);
\draw (notx.output) |- (andz32.input 2);


\end{tikzpicture}

\end{center}

\section{VHDL-Code}
\begin{verbatim}
library ieee;
use ieee.std_logic_1164.all;

entity automat20240125 is
port (
    z3, z2, z1, z0: in std_logic;
    x: in std_logic;
    y1, y0: out std_logic;
    z3s, z2s, z1s, z0s: out std_logic
);
end;

architecture behaviour of automat20240125 is
begin
    z3s <= (z2 and not x) or (z3 and x);
    z2s <= (z0 and not x) or (z2 and x);
    z1s <= (z0 and x) or (z1 and not x);
    z0s <= (z1 and x) or (z3 and not x);
    y1 <= (z0 and not x) or
        (z1 and not x) or
        (z2 and not x) or
        (z2 and x) or
        (z3 and not x);
    y0 <= (z0 and x) or
        (z1 and x) or
        (z2 and x) or
        (z3 and not x);
end;

library ieee;
use ieee.std_logic_1164.all;

entity automat20240125testbench is
port (
    z3, z2, z1, z0: inout std_logic;
    x: inout std_logic;
    y1, y0: inout std_logic;
    z3s, z2s, z1s, z0s: inout std_logic
);
end;

architecture behaviour of automat20240125testbench is
    component automat20240125
    port (
        z3, z2, z1, z0: in std_logic;
        x: in std_logic;
        y1, y0: out std_logic;
        z3s, z2s, z1s, z0s: out std_logic
    );
    end component;
begin
    sn: automat20240125 PORT MAP (z3=>z3, z2=>z2, z1=>z1, z0=>z0, x=>x, y1=>y1, y0=>y0,
        z3s=>z3s, z2s=>z2s, z1s=>z1s, z0s=>z0s);



    z0 <= '1' after 0 ns, '0' after 20 ns;
    z1 <= '0' after 0 ns, '1' after 20 ns, '0' after 40 ns;
    z2 <= '0' after 0 ns, '1' after 40 ns, '0' after 60 ns;
    z3 <= '0' after 0 ns, '1' after 60 ns, '0' after 80 ns;
    x <= '0' after 0 ns, '1' after 10 ns, '0' after 20 ns, '1' after 30 ns, '0'
        after 40 ns, '1' after 50 ns, '0' after 60 ns, '1' after 70 ns, '0' after 80 ns;

end;
\end{verbatim}
\section{GTKWave}
\begin{center}
\includegraphics [width=\textwidth]{gtkwaveautomat20240125.jpeg}
\end{center}
\end{document}
